Data Fields | |
UINT8 | Access |
UINT8 | Reserved1 [7] |
UINT32 | IntEnable |
UINT8 | IntVector |
UINT8 | Reserved2 [3] |
UINT32 | IntSts |
UINT32 | IntfCapability |
UINT8 | Status |
UINT16 | BurstCount |
UINT8 | Reserved3 [9] |
UINT32 | DataFifo |
UINT8 | Reserved4 [0xed8] |
UINT16 | Vid |
UINT16 | Did |
UINT8 | Rid |
UINT8 | TcgDefined [0x7b] |
UINT32 | LegacyAddress1 |
UINT32 | LegacyAddress1Ex |
UINT32 | LegacyAddress2 |
UINT32 | LegacyAddress2Ex |
UINT8 | VendorDefined [0x70] |
UINT8 | StatusEx |
UINT8 TIS_PC_REGISTERS::Access |
Used to gain ownership for this particular port.
UINT16 TIS_PC_REGISTERS::BurstCount |
Number of consecutive writes that can be done to the TPM.
UINT32 TIS_PC_REGISTERS::DataFifo |
Read or write FIFO, depending on transaction.
UINT16 TIS_PC_REGISTERS::Did |
Device ID
UINT32 TIS_PC_REGISTERS::IntEnable |
Controls interrupts.
Shows which interrupts are supported by that particular TPM.
UINT32 TIS_PC_REGISTERS::IntSts |
What caused interrupt.
SIRQ vector to be used by the TPM.
Alias to I/O legacy space.
Additional 8 bits for I/O legacy space extension.
Alias to second I/O legacy space.
Additional 8 bits for second I/O legacy space extension.
UINT8 TIS_PC_REGISTERS::Rid |
Revision ID
UINT8 TIS_PC_REGISTERS::Status |
Status Register. Provides status of the TPM.
TPM2 support CANCEL at BIT[24] of STATUS register (WO)
TCG defined configuration registers.
Vendor-defined configuration registers.
UINT16 TIS_PC_REGISTERS::Vid |
Vendor ID