Defines | |
#define | ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0) |
#define | PCI_TO_PCICFG2_ADDRESS(A) ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32))) |
Functions | |
EFI_PEI_PCI_CFG2_PPI * | InternalGetPciCfg2Ppi (IN UINT64 Address) |
UINT32 | PeiPciSegmentLibPciCfg2ReadWorker (IN UINT64 Address, IN EFI_PEI_PCI_CFG_PPI_WIDTH Width) |
UINT32 | PeiPciSegmentLibPciCfg2WriteWorker (IN UINT64 Address, IN EFI_PEI_PCI_CFG_PPI_WIDTH Width, IN UINT32 Data) |
RETURN_STATUS EFIAPI | PciSegmentRegisterForRuntimeAccess (IN UINTN Address) |
UINT8 EFIAPI | PciSegmentRead8 (IN UINT64 Address) |
UINT8 EFIAPI | PciSegmentWrite8 (IN UINT64 Address, IN UINT8 Value) |
UINT8 EFIAPI | PciSegmentOr8 (IN UINT64 Address, IN UINT8 OrData) |
UINT8 EFIAPI | PciSegmentAnd8 (IN UINT64 Address, IN UINT8 AndData) |
UINT8 EFIAPI | PciSegmentAndThenOr8 (IN UINT64 Address, IN UINT8 AndData, IN UINT8 OrData) |
UINT8 EFIAPI | PciSegmentBitFieldRead8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT8 EFIAPI | PciSegmentBitFieldWrite8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value) |
UINT8 EFIAPI | PciSegmentBitFieldOr8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData) |
UINT8 EFIAPI | PciSegmentBitFieldAnd8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData) |
UINT8 EFIAPI | PciSegmentBitFieldAndThenOr8 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData) |
UINT16 EFIAPI | PciSegmentRead16 (IN UINT64 Address) |
UINT16 EFIAPI | PciSegmentWrite16 (IN UINT64 Address, IN UINT16 Value) |
UINT16 EFIAPI | PciSegmentOr16 (IN UINT64 Address, IN UINT16 OrData) |
UINT16 EFIAPI | PciSegmentAnd16 (IN UINT64 Address, IN UINT16 AndData) |
UINT16 EFIAPI | PciSegmentAndThenOr16 (IN UINT64 Address, IN UINT16 AndData, IN UINT16 OrData) |
UINT16 EFIAPI | PciSegmentBitFieldRead16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT16 EFIAPI | PciSegmentBitFieldWrite16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value) |
UINT16 EFIAPI | PciSegmentBitFieldOr16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData) |
UINT16 EFIAPI | PciSegmentBitFieldAnd16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData) |
UINT16 EFIAPI | PciSegmentBitFieldAndThenOr16 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData) |
UINT32 EFIAPI | PciSegmentRead32 (IN UINT64 Address) |
UINT32 EFIAPI | PciSegmentWrite32 (IN UINT64 Address, IN UINT32 Value) |
UINT32 EFIAPI | PciSegmentOr32 (IN UINT64 Address, IN UINT32 OrData) |
UINT32 EFIAPI | PciSegmentAnd32 (IN UINT64 Address, IN UINT32 AndData) |
UINT32 EFIAPI | PciSegmentAndThenOr32 (IN UINT64 Address, IN UINT32 AndData, IN UINT32 OrData) |
UINT32 EFIAPI | PciSegmentBitFieldRead32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT32 EFIAPI | PciSegmentBitFieldWrite32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value) |
UINT32 EFIAPI | PciSegmentBitFieldOr32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData) |
UINT32 EFIAPI | PciSegmentBitFieldAnd32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData) |
UINT32 EFIAPI | PciSegmentBitFieldAndThenOr32 (IN UINT64 Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData) |
UINTN EFIAPI | PciSegmentReadBuffer (IN UINT64 StartAddress, IN UINTN Size, OUT VOID *Buffer) |
UINTN EFIAPI | PciSegmentWriteBuffer (IN UINT64 StartAddress, IN UINTN Size, IN VOID *Buffer) |
Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS | ( | A, | |||
M | ) | ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0) |
Assert the validity of a PCI Segment address. A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
A | The address to validate. | |
M | Additional bits to assert to be zero. |
#define PCI_TO_PCICFG2_ADDRESS | ( | A | ) | ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32))) |
Translate PCI Lib address into format of PCI CFG2 PPI.
A | The address that encodes the PCI Bus, Device, Function and Register. |
EFI_PEI_PCI_CFG2_PPI* InternalGetPciCfg2Ppi | ( | IN UINT64 | Address | ) |
Gets PCI CFG2 PPI.
This internal function retrieves PCI CFG2 PPI from PPI database.
Address | The address that encodes the PCI Segment, Bus, Device, Function and Register. |
References ASSERT_EFI_ERROR, BitFieldRead64(), gEfiPciCfg2PpiGuid, NULL, PeiServicesLocatePpi(), _EFI_PEI_PCI_CFG2_PPI::Segment, and VOID.
Referenced by PeiPciSegmentLibPciCfg2ReadWorker(), and PeiPciSegmentLibPciCfg2WriteWorker().
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
AndData | The value to AND with the PCI configuration register. |
References PciSegmentRead16(), and PciSegmentWrite16().
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
AndData | The value to AND with the PCI configuration register. |
References PciSegmentRead32(), and PciSegmentWrite32().
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
AndData | The value to AND with the PCI configuration register. |
References PciSegmentRead8(), and PciSegmentWrite8().
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the PCI configuration register. |
References PciSegmentRead16(), and PciSegmentWrite16().
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the PCI configuration register. |
References PciSegmentRead32(), and PciSegmentWrite32().
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the PCI configuration register. |
References PciSegmentRead8(), and PciSegmentWrite8().
UINT16 EFIAPI PciSegmentBitFieldAnd16 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | AndData | |||
) |
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
StartBit | The ordinal of the least significant bit in the bit field. The ordinal of the least significant bit in a byte is bit 0. | |
EndBit | The ordinal of the most significant bit in the bit field. The ordinal of the most significant bit in a byte is bit 7. | |
AndData | The value to AND with the read value from the PCI configuration register. |
References BitFieldAnd16(), PciSegmentRead16(), and PciSegmentWrite16().
UINT32 EFIAPI PciSegmentBitFieldAnd32 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | AndData | |||
) |
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped. If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
AndData | The value to AND with the PCI configuration register. |
References BitFieldAnd32(), PciSegmentRead32(), and PciSegmentWrite32().
UINT8 EFIAPI PciSegmentBitFieldAnd8 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | AndData | |||
) |
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
AndData | The value to AND with the PCI configuration register. |
References BitFieldAnd8(), PciSegmentRead8(), and PciSegmentWrite8().
UINT16 EFIAPI PciSegmentBitFieldAndThenOr16 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | AndData, | |||
IN UINT16 | OrData | |||
) |
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References BitFieldAndThenOr16(), PciSegmentRead16(), and PciSegmentWrite16().
UINT32 EFIAPI PciSegmentBitFieldAndThenOr32 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | AndData, | |||
IN UINT32 | OrData | |||
) |
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References BitFieldAndThenOr32(), PciSegmentRead32(), and PciSegmentWrite32().
UINT8 EFIAPI PciSegmentBitFieldAndThenOr8 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | AndData, | |||
IN UINT8 | OrData | |||
) |
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References BitFieldAndThenOr8(), PciSegmentRead8(), and PciSegmentWrite8().
UINT16 EFIAPI PciSegmentBitFieldOr16 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | OrData | |||
) |
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
OrData | The value to OR with the PCI configuration register. |
References BitFieldOr16(), PciSegmentRead16(), and PciSegmentWrite16().
UINT32 EFIAPI PciSegmentBitFieldOr32 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | OrData | |||
) |
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
OrData | The value to OR with the PCI configuration register. |
References BitFieldOr32(), PciSegmentRead32(), and PciSegmentWrite32().
UINT8 EFIAPI PciSegmentBitFieldOr8 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | OrData | |||
) |
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
OrData | The value to OR with the PCI configuration register. |
References BitFieldOr8(), PciSegmentRead8(), and PciSegmentWrite8().
Reads a bit field of a PCI configuration register.
Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | The PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. |
References BitFieldRead16(), and PciSegmentRead16().
Reads a bit field of a PCI configuration register.
Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | The PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. |
References BitFieldRead32(), and PciSegmentRead32().
Reads a bit field of a PCI configuration register.
Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | The PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. |
References BitFieldRead8(), and PciSegmentRead8().
UINT16 EFIAPI PciSegmentBitFieldWrite16 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
Value | The new value of the bit field. |
References BitFieldWrite16(), PciSegmentRead16(), and PciSegmentWrite16().
UINT32 EFIAPI PciSegmentBitFieldWrite32 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
Value | The new value of the bit field. |
References BitFieldWrite32(), PciSegmentRead32(), and PciSegmentWrite32().
UINT8 EFIAPI PciSegmentBitFieldWrite8 | ( | IN UINT64 | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.
If any reserved bits in Address are set, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
Value | The new value of the bit field. |
References BitFieldWrite8(), PciSegmentRead8(), and PciSegmentWrite8().
Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function and Register. | |
OrData | The value to OR with the PCI configuration register. |
References PciSegmentRead16(), and PciSegmentWrite16().
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
OrData | The value to OR with the PCI configuration register. |
References PciSegmentRead32(), and PciSegmentWrite32().
Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
OrData | The value to OR with the PCI configuration register. |
References PciSegmentRead8(), and PciSegmentWrite8().
Reads a 16-bit PCI configuration register.
Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. |
References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, EfiPeiPciCfgWidthUint16, and PeiPciSegmentLibPciCfg2ReadWorker().
Reads a 32-bit PCI configuration register.
Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. |
References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, EfiPeiPciCfgWidthUint32, and PeiPciSegmentLibPciCfg2ReadWorker().
Reads an 8-bit PCI configuration register.
Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. |
References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, EfiPeiPciCfgWidthUint8, and PeiPciSegmentLibPciCfg2ReadWorker().
Reads a range of PCI configuration registers into a caller supplied buffer.
Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.
If any reserved bits in StartAddress are set, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
StartAddress | The starting address that encodes the PCI Segment, Bus, Device, Function and Register. | |
Size | The size in bytes of the transfer. | |
Buffer | The pointer to a buffer receiving the data read. |
References ASSERT, ASSERT_INVALID_PCI_SEGMENT_ADDRESS, BIT0, BIT1, NULL, PciSegmentRead16(), PciSegmentRead32(), PciSegmentRead8(), WriteUnaligned16(), and WriteUnaligned32().
RETURN_STATUS EFIAPI PciSegmentRegisterForRuntimeAccess | ( | IN UINTN | Address | ) |
Register a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().
If any reserved bits in Address are set, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. |
RETURN_SUCCESS | The PCI device was registered for runtime access. | |
RETURN_UNSUPPORTED | An attempt was made to call this function after ExitBootServices(). | |
RETURN_UNSUPPORTED | The resources required to access the PCI device at runtime could not be mapped. | |
RETURN_OUT_OF_RESOURCES | There are not enough resources available to complete the registration. |
References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, and RETURN_UNSUPPORTED.
Writes a 16-bit PCI configuration register.
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
Value | The value to write. |
References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, EfiPeiPciCfgWidthUint16, and PeiPciSegmentLibPciCfg2WriteWorker().
Writes a 32-bit PCI configuration register.
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
Value | The value to write. |
References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, EfiPeiPciCfgWidthUint32, and PeiPciSegmentLibPciCfg2WriteWorker().
Writes an 8-bit PCI configuration register.
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
Address | The address that encodes the PCI Segment, Bus, Device, Function, and Register. | |
Value | The value to write. |
References ASSERT_INVALID_PCI_SEGMENT_ADDRESS, EfiPeiPciCfgWidthUint8, and PeiPciSegmentLibPciCfg2WriteWorker().
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.
If any reserved bits in StartAddress are set, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
StartAddress | The starting address that encodes the PCI Segment, Bus, Device, Function and Register. | |
Size | The size in bytes of the transfer. | |
Buffer | The pointer to a buffer containing the data to write. |
References ASSERT, ASSERT_INVALID_PCI_SEGMENT_ADDRESS, BIT0, BIT1, NULL, PciSegmentWrite16(), PciSegmentWrite32(), PciSegmentWrite8(), ReadUnaligned16(), and ReadUnaligned32().
UINT32 PeiPciSegmentLibPciCfg2ReadWorker | ( | IN UINT64 | Address, | |
IN EFI_PEI_PCI_CFG_PPI_WIDTH | Width | |||
) |
Internal worker function to read a PCI configuration register.
This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service. It reads and returns the PCI configuration register specified by Address, the width of data is specified by Width.
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
Width | The width of data to read |
References CONST, GetPeiServicesTablePointer(), InternalGetPciCfg2Ppi(), and PCI_TO_PCICFG2_ADDRESS.
Referenced by PciSegmentRead16(), PciSegmentRead32(), and PciSegmentRead8().
UINT32 PeiPciSegmentLibPciCfg2WriteWorker | ( | IN UINT64 | Address, | |
IN EFI_PEI_PCI_CFG_PPI_WIDTH | Width, | |||
IN UINT32 | Data | |||
) |
Internal worker function to writes a PCI configuration register.
This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service. It writes the PCI configuration register specified by Address with the value specified by Data. The width of data is specifed by Width. Data is returned.
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
Width | The width of data to write | |
Data | The value to write. |
References CONST, GetPeiServicesTablePointer(), InternalGetPciCfg2Ppi(), and PCI_TO_PCICFG2_ADDRESS.
Referenced by PciSegmentWrite16(), PciSegmentWrite32(), and PciSegmentWrite8().