Data Fields | |
UINT8 | Reserved1 [248] |
UINT32 | SMBASE |
UINT32 | SMMRevId |
UINT16 | IORestart |
UINT16 | AutoHALTRestart |
UINT8 | Reserved2 [164] |
UINT32 | ES |
UINT32 | CS |
UINT32 | SS |
UINT32 | DS |
UINT32 | FS |
UINT32 | GS |
UINT32 | LDTBase |
UINT32 | TR |
UINT32 | DR7 |
UINT32 | DR6 |
UINT32 | EAX |
UINT32 | ECX |
UINT32 | EDX |
UINT32 | EBX |
UINT32 | ESP |
UINT32 | EBP |
UINT32 | ESI |
UINT32 | EDI |
UINT32 | EIP |
UINT32 | EFLAGS |
UINT32 | CR3 |
UINT32 | CR0 |
Describes behavior that should be commenced in response to a halt instruction.
UINT32 EFI_SMI_CPU_SAVE_STATE::CR0 |
UINT32 EFI_SMI_CPU_SAVE_STATE::CR3 |
UINT32 EFI_SMI_CPU_SAVE_STATE::CS |
UINT32 EFI_SMI_CPU_SAVE_STATE::DR6 |
UINT32 EFI_SMI_CPU_SAVE_STATE::DR7 |
UINT32 EFI_SMI_CPU_SAVE_STATE::DS |
UINT32 EFI_SMI_CPU_SAVE_STATE::EAX |
UINT32 EFI_SMI_CPU_SAVE_STATE::EBP |
UINT32 EFI_SMI_CPU_SAVE_STATE::EBX |
UINT32 EFI_SMI_CPU_SAVE_STATE::ECX |
UINT32 EFI_SMI_CPU_SAVE_STATE::EDI |
UINT32 EFI_SMI_CPU_SAVE_STATE::EDX |
UINT32 EFI_SMI_CPU_SAVE_STATE::EIP |
UINT32 EFI_SMI_CPU_SAVE_STATE::ES |
UINT32 EFI_SMI_CPU_SAVE_STATE::ESI |
UINT32 EFI_SMI_CPU_SAVE_STATE::ESP |
UINT32 EFI_SMI_CPU_SAVE_STATE::FS |
UINT32 EFI_SMI_CPU_SAVE_STATE::GS |
The value of the I/O restart field. Allows for restarting an in-process I/O instruction.
UINT8 EFI_SMI_CPU_SAVE_STATE::Reserved1[248] |
Reserved for future processors. As such, software should not attempt to interpret or write to this region.
UINT8 EFI_SMI_CPU_SAVE_STATE::Reserved2[164] |
Reserved for future processors. As such, software should not attempt to interpret or write to this region.
The location of the processor SMBASE, which is the location where the processor will pass control upon receipt of an SMI.
The revision of the SMM save state. This value is set by the processor.
UINT32 EFI_SMI_CPU_SAVE_STATE::SS |
UINT32 EFI_SMI_CPU_SAVE_STATE::TR |