MdePkg/Include/Library/PciLib.h File Reference


Defines

#define PCI_LIB_ADDRESS(Bus, Device, Function, Register)   (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))

Functions

RETURN_STATUS EFIAPI PciRegisterForRuntimeAccess (IN UINTN Address)
UINT8 EFIAPI PciRead8 (IN UINTN Address)
UINT8 EFIAPI PciWrite8 (IN UINTN Address, IN UINT8 Value)
UINT8 EFIAPI PciOr8 (IN UINTN Address, IN UINT8 OrData)
UINT8 EFIAPI PciAnd8 (IN UINTN Address, IN UINT8 AndData)
UINT8 EFIAPI PciAndThenOr8 (IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData)
UINT8 EFIAPI PciBitFieldRead8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT8 EFIAPI PciBitFieldWrite8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value)
UINT8 EFIAPI PciBitFieldOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData)
UINT8 EFIAPI PciBitFieldAnd8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData)
UINT8 EFIAPI PciBitFieldAndThenOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData)
UINT16 EFIAPI PciRead16 (IN UINTN Address)
UINT16 EFIAPI PciWrite16 (IN UINTN Address, IN UINT16 Value)
UINT16 EFIAPI PciOr16 (IN UINTN Address, IN UINT16 OrData)
UINT16 EFIAPI PciAnd16 (IN UINTN Address, IN UINT16 AndData)
UINT16 EFIAPI PciAndThenOr16 (IN UINTN Address, IN UINT16 AndData, IN UINT16 OrData)
UINT16 EFIAPI PciBitFieldRead16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT16 EFIAPI PciBitFieldWrite16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value)
UINT16 EFIAPI PciBitFieldOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData)
UINT16 EFIAPI PciBitFieldAnd16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData)
UINT16 EFIAPI PciBitFieldAndThenOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData)
UINT32 EFIAPI PciRead32 (IN UINTN Address)
UINT32 EFIAPI PciWrite32 (IN UINTN Address, IN UINT32 Value)
UINT32 EFIAPI PciOr32 (IN UINTN Address, IN UINT32 OrData)
UINT32 EFIAPI PciAnd32 (IN UINTN Address, IN UINT32 AndData)
UINT32 EFIAPI PciAndThenOr32 (IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData)
UINT32 EFIAPI PciBitFieldRead32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT32 EFIAPI PciBitFieldWrite32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value)
UINT32 EFIAPI PciBitFieldOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData)
UINT32 EFIAPI PciBitFieldAnd32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData)
UINT32 EFIAPI PciBitFieldAndThenOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData)
UINTN EFIAPI PciReadBuffer (IN UINTN StartAddress, IN UINTN Size, OUT VOID *Buffer)
UINTN EFIAPI PciWriteBuffer (IN UINTN StartAddress, IN UINTN Size, IN VOID *Buffer)

Detailed Description

Provides services to access PCI Configuration Space.

These functions perform PCI configuration cycles using the default PCI configuration access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate access method. Modules will typically use the PCI Library for its PCI configuration accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or PCI Express Library may be used in conjunction with the PCI Library. The functionality of these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use explicit access methods.

Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.


Define Documentation

#define PCI_LIB_ADDRESS ( Bus,
Device,
Function,
Register   )     (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))

Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an address that can be passed to the PCI Library functions.

Parameters:
Bus PCI Bus number. Range 0..255.
Device PCI Device number. Range 0..31.
Function PCI Function number. Range 0..7.
Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
Returns:
The encoded PCI address.


Function Documentation

UINT16 EFIAPI PciAnd16 ( IN UINTN  Address,
IN UINT16  AndData 
)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References PciCf8And16(), PciExpressAnd16(), PciRead16(), and PciWrite16().

Referenced by S3PciAnd16().

UINT32 EFIAPI PciAnd32 ( IN UINTN  Address,
IN UINT32  AndData 
)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References PciCf8And32(), PciExpressAnd32(), PciRead32(), and PciWrite32().

Referenced by S3PciAnd32().

UINT8 EFIAPI PciAnd8 ( IN UINTN  Address,
IN UINT8  AndData 
)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References PciCf8And8(), PciExpressAnd8(), PciRead8(), and PciWrite8().

Referenced by S3PciAnd8().

UINT16 EFIAPI PciAndThenOr16 ( IN UINTN  Address,
IN UINT16  AndData,
IN UINT16  OrData 
)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References PciCf8AndThenOr16(), PciExpressAndThenOr16(), PciRead16(), and PciWrite16().

Referenced by S3PciAndThenOr16().

UINT32 EFIAPI PciAndThenOr32 ( IN UINTN  Address,
IN UINT32  AndData,
IN UINT32  OrData 
)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References PciCf8AndThenOr32(), PciExpressAndThenOr32(), PciRead32(), and PciWrite32().

Referenced by S3PciAndThenOr32().

UINT8 EFIAPI PciAndThenOr8 ( IN UINTN  Address,
IN UINT8  AndData,
IN UINT8  OrData 
)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed by a bitwise OR with another 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References PciCf8AndThenOr8(), PciExpressAndThenOr8(), PciRead8(), and PciWrite8().

Referenced by S3PciAndThenOr8().

UINT16 EFIAPI PciBitFieldAnd16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  AndData 
)

Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldAnd16(), PciCf8BitFieldAnd16(), PciExpressBitFieldAnd16(), PciRead16(), and PciWrite16().

Referenced by S3PciBitFieldAnd16().

UINT32 EFIAPI PciBitFieldAnd32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  AndData 
)

Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldAnd32(), PciCf8BitFieldAnd32(), PciExpressBitFieldAnd32(), PciRead32(), and PciWrite32().

Referenced by S3PciBitFieldAnd32().

UINT8 EFIAPI PciBitFieldAnd8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  AndData 
)

Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldAnd8(), PciCf8BitFieldAnd8(), PciExpressBitFieldAnd8(), PciRead8(), and PciWrite8().

Referenced by S3PciBitFieldAnd8().

UINT16 EFIAPI PciBitFieldAndThenOr16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  AndData,
IN UINT16  OrData 
)

Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References BitFieldAndThenOr16(), PciCf8BitFieldAndThenOr16(), PciExpressBitFieldAndThenOr16(), PciRead16(), and PciWrite16().

Referenced by S3PciBitFieldAndThenOr16().

UINT32 EFIAPI PciBitFieldAndThenOr32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  AndData,
IN UINT32  OrData 
)

Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References BitFieldAndThenOr32(), PciCf8BitFieldAndThenOr32(), PciExpressBitFieldAndThenOr32(), PciRead32(), and PciWrite32().

Referenced by S3PciBitFieldAndThenOr32().

UINT8 EFIAPI PciBitFieldAndThenOr8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  AndData,
IN UINT8  OrData 
)

Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
AndData The value to AND with the PCI configuration register.
OrData The value to OR with the result of the AND operation.
Returns:
The value written back to the PCI configuration register.

References BitFieldAndThenOr8(), PciCf8BitFieldAndThenOr8(), PciExpressBitFieldAndThenOr8(), PciRead8(), and PciWrite8().

Referenced by S3PciBitFieldAndThenOr8().

UINT16 EFIAPI PciBitFieldOr16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  OrData 
)

Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldOr16(), PciCf8BitFieldOr16(), PciExpressBitFieldOr16(), PciRead16(), and PciWrite16().

Referenced by S3PciBitFieldOr16().

UINT32 EFIAPI PciBitFieldOr32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  OrData 
)

Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldOr32(), PciCf8BitFieldOr32(), PciExpressBitFieldOr32(), PciRead32(), and PciWrite32().

Referenced by S3PciBitFieldOr32().

UINT8 EFIAPI PciBitFieldOr8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  OrData 
)

Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References BitFieldOr8(), PciCf8BitFieldOr8(), PciExpressBitFieldOr8(), PciRead8(), and PciWrite8().

Referenced by S3PciBitFieldOr8().

UINT16 EFIAPI PciBitFieldRead16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Returns:
The value of the bit field read from the PCI configuration register.
Reads a bit field of a PCI configuration register.

Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Returns:
The value of the bit field read from the PCI configuration register.

References BitFieldRead16(), PciCf8BitFieldRead16(), PciExpressBitFieldRead16(), and PciRead16().

Referenced by S3PciBitFieldRead16().

UINT32 EFIAPI PciBitFieldRead32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Returns:
The value of the bit field read from the PCI configuration register.
Reads a bit field of a PCI configuration register.

Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Returns:
The value of the bit field read from the PCI configuration register.

References BitFieldRead32(), PciCf8BitFieldRead32(), PciExpressBitFieldRead32(), and PciRead32().

Referenced by S3PciBitFieldRead32().

UINT8 EFIAPI PciBitFieldRead8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit 
)

Reads a bit field of a PCI configuration register.

Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Returns:
The value of the bit field read from the PCI configuration register.
Reads a bit field of a PCI configuration register.

Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters:
Address The PCI configuration register to read.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Returns:
The value of the bit field read from the PCI configuration register.

References BitFieldRead8(), PciCf8BitFieldRead8(), PciExpressBitFieldRead8(), and PciRead8().

Referenced by S3PciBitFieldRead8().

UINT16 EFIAPI PciBitFieldWrite16 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT16  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Value New value of the bit field.
Returns:
The value written back to the PCI configuration register.
Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit The ordinal of the most significant bit in the bit field. Range 0..15.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References BitFieldWrite16(), PciCf8BitFieldWrite16(), PciExpressBitFieldWrite16(), PciRead16(), and PciWrite16().

Referenced by S3PciBitFieldWrite16().

UINT32 EFIAPI PciBitFieldWrite32 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT32  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Value New value of the bit field.
Returns:
The value written back to the PCI configuration register.
Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit The ordinal of the most significant bit in the bit field. Range 0..31.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References BitFieldWrite32(), PciCf8BitFieldWrite32(), PciExpressBitFieldWrite32(), PciRead32(), and PciWrite32().

Referenced by S3PciBitFieldWrite32().

UINT8 EFIAPI PciBitFieldWrite8 ( IN UINTN  Address,
IN UINTN  StartBit,
IN UINTN  EndBit,
IN UINT8  Value 
)

Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Value New value of the bit field.
Returns:
The value written back to the PCI configuration register.
Writes a bit field to a PCI configuration register.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters:
Address The PCI configuration register to write.
StartBit The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit The ordinal of the most significant bit in the bit field. Range 0..7.
Value The new value of the bit field.
Returns:
The value written back to the PCI configuration register.

References BitFieldWrite8(), PciCf8BitFieldWrite8(), PciExpressBitFieldWrite8(), PciRead8(), and PciWrite8().

Referenced by S3PciBitFieldWrite8().

UINT16 EFIAPI PciOr16 ( IN UINTN  Address,
IN UINT16  OrData 
)

Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References PciCf8Or16(), PciExpressOr16(), PciRead16(), and PciWrite16().

Referenced by S3PciOr16().

UINT32 EFIAPI PciOr32 ( IN UINTN  Address,
IN UINT32  OrData 
)

Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References PciCf8Or32(), PciExpressOr32(), PciRead32(), and PciWrite32().

Referenced by S3PciOr32().

UINT8 EFIAPI PciOr8 ( IN UINTN  Address,
IN UINT8  OrData 
)

Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.
Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
OrData The value to OR with the PCI configuration register.
Returns:
The value written back to the PCI configuration register.

References PciCf8Or8(), PciExpressOr8(), PciRead8(), and PciWrite8().

Referenced by S3PciOr8().

UINT16 EFIAPI PciRead16 ( IN UINTN  Address  ) 

Reads a 16-bit PCI configuration register.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads a 16-bit PCI configuration register.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads a 16-bit PCI configuration register.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The value read from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, DxePciLibEsalReadWorker(), DxePciLibPciRootBridgeIoReadWorker(), EfiPciWidthUint16, EfiPeiPciCfgWidthUint16, PciCf8Read16(), PciExpressRead16(), PeiPciLibPciCfg2ReadWorker(), and SmmPciLibPciRootBridgeIoReadWorker().

Referenced by PciAnd16(), PciAndThenOr16(), PciBitFieldAnd16(), PciBitFieldAndThenOr16(), PciBitFieldOr16(), PciBitFieldRead16(), PciBitFieldWrite16(), PciOr16(), PciReadBuffer(), and S3PciRead16().

UINT32 EFIAPI PciRead32 ( IN UINTN  Address  ) 

Reads a 32-bit PCI configuration register.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads a 32-bit PCI configuration register.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads a 32-bit PCI configuration register.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The value read from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, DxePciLibEsalReadWorker(), DxePciLibPciRootBridgeIoReadWorker(), EfiPciWidthUint32, EfiPeiPciCfgWidthUint32, PciCf8Read32(), PciExpressRead32(), PeiPciLibPciCfg2ReadWorker(), and SmmPciLibPciRootBridgeIoReadWorker().

Referenced by PciAnd32(), PciAndThenOr32(), PciBitFieldAnd32(), PciBitFieldAndThenOr32(), PciBitFieldOr32(), PciBitFieldRead32(), PciBitFieldWrite32(), PciOr32(), PciReadBuffer(), and S3PciRead32().

UINT8 EFIAPI PciRead8 ( IN UINTN  Address  ) 

Reads an 8-bit PCI configuration register.

Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads an 8-bit PCI configuration register.

Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Returns:
The read value from the PCI configuration register.
Reads an 8-bit PCI configuration register.

Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Returns:
The value read from the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, DxePciLibEsalReadWorker(), DxePciLibPciRootBridgeIoReadWorker(), EfiPciWidthUint8, EfiPeiPciCfgWidthUint8, PciCf8Read8(), PciExpressRead8(), PeiPciLibPciCfg2ReadWorker(), and SmmPciLibPciRootBridgeIoReadWorker().

Referenced by PciAnd8(), PciAndThenOr8(), PciBitFieldAnd8(), PciBitFieldAndThenOr8(), PciBitFieldOr8(), PciBitFieldRead8(), PciBitFieldWrite8(), PciOr8(), PciReadBuffer(), and S3PciRead8().

UINTN EFIAPI PciReadBuffer ( IN UINTN  StartAddress,
IN UINTN  Size,
OUT VOID *  Buffer 
)

Reads a range of PCI configuration registers into a caller supplied buffer.

Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress Starting address that encodes the PCI Bus, Device, Function and Register.
Size Size in bytes of the transfer.
Buffer Pointer to a buffer receiving the data read.
Returns:
Size
Reads a range of PCI configuration registers into a caller supplied buffer.

Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress The starting address that encodes the PCI Bus, Device, Function and Register.
Size The size in bytes of the transfer.
Buffer The pointer to a buffer receiving the data read.
Returns:
Size

References ASSERT, ASSERT_INVALID_PCI_ADDRESS, BIT0, BIT1, NULL, PciCf8ReadBuffer(), PciExpressReadBuffer(), PciRead16(), PciRead32(), PciRead8(), WriteUnaligned16(), and WriteUnaligned32().

Referenced by S3PciReadBuffer().

RETURN_STATUS EFIAPI PciRegisterForRuntimeAccess ( IN UINTN  Address  ) 

Registers a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().

Registers the PCI device specified by Address so all the PCI configuration registers associated with that PCI device may be accessed after SetVirtualAddressMap() is called.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Return values:
RETURN_SUCCESS The PCI device was registered for runtime access.
RETURN_UNSUPPORTED An attempt was made to call this function after ExitBootServices().
RETURN_UNSUPPORTED The resources required to access the PCI device at runtime could not be mapped.
RETURN_OUT_OF_RESOURCES There are not enough resources available to complete the registration.
Registers a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().

Registers the PCI device specified by Address so all the PCI configuration registers associated with that PCI device may be accessed after SetVirtualAddressMap() is called.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Return values:
RETURN_SUCCESS The PCI device was registered for runtime access.
RETURN_UNSUPPORTED An attempt was made to call this function after ExitBootServices().
RETURN_UNSUPPORTED The resources required to access the PCI device at runtime could not be mapped.
RETURN_OUT_OF_RESOURCES There are not enough resources available to complete the registration.
Register a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Return values:
RETURN_SUCCESS The PCI device was registered for runtime access.
RETURN_UNSUPPORTED An attempt was made to call this function after ExitBootServices().
RETURN_UNSUPPORTED The resources required to access the PCI device at runtime could not be mapped.
RETURN_OUT_OF_RESOURCES There are not enough resources available to complete the registration.

References ASSERT_INVALID_PCI_ADDRESS, PciCf8RegisterForRuntimeAccess(), PciExpressRegisterForRuntimeAccess(), RETURN_SUCCESS, and RETURN_UNSUPPORTED.

UINT16 EFIAPI PciWrite16 ( IN UINTN  Address,
IN UINT16  Value 
)

Writes a 16-bit PCI configuration register.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes a 16-bit PCI configuration register.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes a 16-bit PCI configuration register.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Data The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, DxePciLibEsalWriteWorker(), DxePciLibPciRootBridgeIoWriteWorker(), EfiPciWidthUint16, EfiPeiPciCfgWidthUint16, PciCf8Write16(), PciExpressWrite16(), PeiPciLibPciCfg2WriteWorker(), and SmmPciLibPciRootBridgeIoWriteWorker().

Referenced by PciAnd16(), PciAndThenOr16(), PciBitFieldAnd16(), PciBitFieldAndThenOr16(), PciBitFieldOr16(), PciBitFieldWrite16(), PciOr16(), PciWriteBuffer(), and S3PciWrite16().

UINT32 EFIAPI PciWrite32 ( IN UINTN  Address,
IN UINT32  Value 
)

Writes a 32-bit PCI configuration register.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes a 32-bit PCI configuration register.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes a 32-bit PCI configuration register.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Data The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, DxePciLibEsalWriteWorker(), DxePciLibPciRootBridgeIoWriteWorker(), EfiPciWidthUint32, EfiPeiPciCfgWidthUint32, PciCf8Write32(), PciExpressWrite32(), PeiPciLibPciCfg2WriteWorker(), and SmmPciLibPciRootBridgeIoWriteWorker().

Referenced by PciAnd32(), PciAndThenOr32(), PciBitFieldAnd32(), PciBitFieldAndThenOr32(), PciBitFieldOr32(), PciBitFieldWrite32(), PciOr32(), PciWriteBuffer(), and S3PciWrite32().

UINT8 EFIAPI PciWrite8 ( IN UINTN  Address,
IN UINT8  Value 
)

Writes an 8-bit PCI configuration register.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes an 8-bit PCI configuration register.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address The address that encodes the PCI Bus, Device, Function and Register.
Value The value to write.
Returns:
The value written to the PCI configuration register.
Writes an 8-bit PCI configuration register.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters:
Address Address that encodes the PCI Bus, Device, Function and Register.
Data The value to write.
Returns:
The value written to the PCI configuration register.

References ASSERT_INVALID_PCI_ADDRESS, DxePciLibEsalWriteWorker(), DxePciLibPciRootBridgeIoWriteWorker(), EfiPciWidthUint8, EfiPeiPciCfgWidthUint8, PciCf8Write8(), PciExpressWrite8(), PeiPciLibPciCfg2WriteWorker(), and SmmPciLibPciRootBridgeIoWriteWorker().

Referenced by PciAnd8(), PciAndThenOr8(), PciBitFieldAnd8(), PciBitFieldAndThenOr8(), PciBitFieldOr8(), PciBitFieldWrite8(), PciOr8(), PciWriteBuffer(), and S3PciWrite8().

UINTN EFIAPI PciWriteBuffer ( IN UINTN  StartAddress,
IN UINTN  Size,
IN VOID *  Buffer 
)

Copies the data in a caller supplied buffer to a specified range of PCI configuration space.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress Starting address that encodes the PCI Bus, Device, Function and Register.
Size Size in bytes of the transfer.
Buffer Pointer to a buffer containing the data to write.
Returns:
Size written to StartAddress.
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress The starting address that encodes the PCI Bus, Device, Function and Register.
Size The size in bytes of the transfer.
Buffer The pointer to a buffer containing the data to write.
Returns:
Size written to StartAddress.
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters:
StartAddress Starting address that encodes the PCI Bus, Device, Function and Register.
Size Size in bytes of the transfer.
Buffer Pointer to a buffer containing the data to write.
Returns:
Size

References ASSERT, ASSERT_INVALID_PCI_ADDRESS, BIT0, BIT1, NULL, PciCf8WriteBuffer(), PciExpressWriteBuffer(), PciWrite16(), PciWrite32(), PciWrite8(), ReadUnaligned16(), and ReadUnaligned32().

Referenced by S3PciWriteBuffer().


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