EFI_SMI_CPU_SAVE_STATE Struct Reference


Data Fields

UINT8 Reserved1 [248]
UINT32 SMBASE
UINT32 SMMRevId
UINT16 IORestart
UINT16 AutoHALTRestart
UINT8 Reserved2 [164]
UINT32 ES
UINT32 CS
UINT32 SS
UINT32 DS
UINT32 FS
UINT32 GS
UINT32 LDTBase
UINT32 TR
UINT32 DR7
UINT32 DR6
UINT32 EAX
UINT32 ECX
UINT32 EDX
UINT32 EBX
UINT32 ESP
UINT32 EBP
UINT32 ESI
UINT32 EDI
UINT32 EIP
UINT32 EFLAGS
UINT32 CR3
UINT32 CR0

Detailed Description

The processor save-state information for IA-32 processors. This information is important in that the SMM drivers may need to ascertain the state of the processor before invoking the SMI.

Field Documentation

Describes behavior that should be commenced in response to a halt instruction.

The value of the I/O restart field. Allows for restarting an in-process I/O instruction.

Reserved for future processors. As such, software should not attempt to interpret or write to this region.

Reserved for future processors. As such, software should not attempt to interpret or write to this region.

The location of the processor SMBASE, which is the location where the processor will pass control upon receipt of an SMI.

The revision of the SMM save state. This value is set by the processor.


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