Functions | |
VOID EFIAPI | DxeRuntimePciExpressLibVirtualNotify (IN EFI_EVENT Event, IN VOID *Context) |
EFI_STATUS EFIAPI | DxeRuntimePciExpressLibConstructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) |
EFI_STATUS EFIAPI | DxeRuntimePciExpressLibDestructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) |
UINTN | GetPciExpressAddress (IN UINTN Address) |
RETURN_STATUS EFIAPI | PciExpressRegisterForRuntimeAccess (IN UINTN Address) |
UINT8 EFIAPI | PciExpressRead8 (IN UINTN Address) |
UINT8 EFIAPI | PciExpressWrite8 (IN UINTN Address, IN UINT8 Value) |
UINT8 EFIAPI | PciExpressOr8 (IN UINTN Address, IN UINT8 OrData) |
UINT8 EFIAPI | PciExpressAnd8 (IN UINTN Address, IN UINT8 AndData) |
UINT8 EFIAPI | PciExpressAndThenOr8 (IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData) |
UINT8 EFIAPI | PciExpressBitFieldRead8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT8 EFIAPI | PciExpressBitFieldWrite8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value) |
UINT8 EFIAPI | PciExpressBitFieldOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData) |
UINT8 EFIAPI | PciExpressBitFieldAnd8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData) |
UINT8 EFIAPI | PciExpressBitFieldAndThenOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData) |
UINT16 EFIAPI | PciExpressRead16 (IN UINTN Address) |
UINT16 EFIAPI | PciExpressWrite16 (IN UINTN Address, IN UINT16 Value) |
UINT16 EFIAPI | PciExpressOr16 (IN UINTN Address, IN UINT16 OrData) |
UINT16 EFIAPI | PciExpressAnd16 (IN UINTN Address, IN UINT16 AndData) |
UINT16 EFIAPI | PciExpressAndThenOr16 (IN UINTN Address, IN UINT16 AndData, IN UINT16 OrData) |
UINT16 EFIAPI | PciExpressBitFieldRead16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT16 EFIAPI | PciExpressBitFieldWrite16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value) |
UINT16 EFIAPI | PciExpressBitFieldOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData) |
UINT16 EFIAPI | PciExpressBitFieldAnd16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData) |
UINT16 EFIAPI | PciExpressBitFieldAndThenOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData) |
UINT32 EFIAPI | PciExpressRead32 (IN UINTN Address) |
UINT32 EFIAPI | PciExpressWrite32 (IN UINTN Address, IN UINT32 Value) |
UINT32 EFIAPI | PciExpressOr32 (IN UINTN Address, IN UINT32 OrData) |
UINT32 EFIAPI | PciExpressAnd32 (IN UINTN Address, IN UINT32 AndData) |
UINT32 EFIAPI | PciExpressAndThenOr32 (IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData) |
UINT32 EFIAPI | PciExpressBitFieldRead32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit) |
UINT32 EFIAPI | PciExpressBitFieldWrite32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value) |
UINT32 EFIAPI | PciExpressBitFieldOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData) |
UINT32 EFIAPI | PciExpressBitFieldAnd32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData) |
UINT32 EFIAPI | PciExpressBitFieldAndThenOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData) |
UINTN EFIAPI | PciExpressReadBuffer (IN UINTN StartAddress, IN UINTN Size, OUT VOID *Buffer) |
UINTN EFIAPI | PciExpressWriteBuffer (IN UINTN StartAddress, IN UINTN Size, IN VOID *Buffer) |
Variables | |
EFI_EVENT | mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL |
UINTN | mDxeRuntimePciExpressLibPciExpressBaseAddress = 0 |
UINTN | mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0 |
PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE * | mDxeRuntimePciExpressLibRegistrationTable = NULL |
UINTN | mDxeRuntimePciExpressLibLastRuntimeRange = 0 |
All assertions for I/O operations are handled in MMIO functions in the IoLib Library.
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
EFI_STATUS EFIAPI DxeRuntimePciExpressLibConstructor | ( | IN EFI_HANDLE | ImageHandle, | |
IN EFI_SYSTEM_TABLE * | SystemTable | |||
) |
The constructor function caches the PCI Express Base Address and creates a Set Virtual Address Map event to convert physical address to virtual addresses.
ImageHandle | The firmware allocated handle for the EFI image. | |
SystemTable | A pointer to the EFI System Table. |
EFI_SUCCESS | The constructor completed successfully. | |
Other | value The constructor did not complete successfully. |
References ASSERT_EFI_ERROR, EFI_BOOT_SERVICES::CreateEventEx, DxeRuntimePciExpressLibVirtualNotify(), EVT_NOTIFY_SIGNAL, gBS, gEfiEventVirtualAddressChangeGuid, mDxeRuntimePciExpressLibPciExpressBaseAddress, mDxeRuntimePciExpressLibVirtualNotifyEvent, NULL, PcdGet64, and TPL_NOTIFY.
EFI_STATUS EFIAPI DxeRuntimePciExpressLibDestructor | ( | IN EFI_HANDLE | ImageHandle, | |
IN EFI_SYSTEM_TABLE * | SystemTable | |||
) |
The destructor function frees any allocated buffers and closes the Set Virtual Address Map event.
ImageHandle | The firmware allocated handle for the EFI image. | |
SystemTable | A pointer to the EFI System Table. |
EFI_SUCCESS | The destructor completed successfully. | |
Other | value The destructor did not complete successfully. |
References ASSERT_EFI_ERROR, EFI_BOOT_SERVICES::CloseEvent, FreePool(), gBS, mDxeRuntimePciExpressLibRegistrationTable, mDxeRuntimePciExpressLibVirtualNotifyEvent, and NULL.
Convert the physical PCI Express MMIO addresses for all registered PCI devices to virtual addresses.
[in] | Event | The event that is being processed. |
[in] | Context | The Event Context. |
References EfiConvertPointer(), mDxeRuntimePciExpressLibNumberOfRuntimeRanges, mDxeRuntimePciExpressLibRegistrationTable, NULL, and VOID.
Referenced by DxeRuntimePciExpressLibConstructor().
UINTN GetPciExpressAddress | ( | IN UINTN | Address | ) |
Gets the base address of PCI Express.
This internal functions retrieves PCI Express Base Address via a PCD entry PcdPciExpressBaseAddress.
Address | The address that encodes the PCI Bus, Device, Function and Register. |
References ASSERT, CpuBreakpoint(), EfiGoneVirtual(), FALSE, mDxeRuntimePciExpressLibLastRuntimeRange, mDxeRuntimePciExpressLibNumberOfRuntimeRanges, mDxeRuntimePciExpressLibPciExpressBaseAddress, and mDxeRuntimePciExpressLibRegistrationTable.
Referenced by PciExpressAnd16(), PciExpressAnd32(), PciExpressAnd8(), PciExpressAndThenOr16(), PciExpressAndThenOr32(), PciExpressAndThenOr8(), PciExpressBitFieldAnd16(), PciExpressBitFieldAnd32(), PciExpressBitFieldAnd8(), PciExpressBitFieldAndThenOr16(), PciExpressBitFieldAndThenOr32(), PciExpressBitFieldAndThenOr8(), PciExpressBitFieldOr16(), PciExpressBitFieldOr32(), PciExpressBitFieldOr8(), PciExpressBitFieldRead16(), PciExpressBitFieldRead32(), PciExpressBitFieldRead8(), PciExpressBitFieldWrite16(), PciExpressBitFieldWrite32(), PciExpressBitFieldWrite8(), PciExpressOr16(), PciExpressOr32(), PciExpressOr8(), PciExpressRead16(), PciExpressRead32(), PciExpressRead8(), PciExpressRegisterForRuntimeAccess(), PciExpressWrite16(), PciExpressWrite32(), and PciExpressWrite8().
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. |
References GetPciExpressAddress(), and MmioAnd16().
Referenced by PciAnd16().
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. |
References GetPciExpressAddress(), and MmioAnd32().
Referenced by PciAnd32().
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. |
References GetPciExpressAddress(), and MmioAnd8().
Referenced by PciAnd8().
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References GetPciExpressAddress(), and MmioAndThenOr16().
Referenced by PciAndThenOr16().
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References GetPciExpressAddress(), and MmioAndThenOr32().
Referenced by PciAndThenOr32().
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References GetPciExpressAddress(), and MmioAndThenOr8().
Referenced by PciAndThenOr8().
UINT16 EFIAPI PciExpressBitFieldAnd16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | AndData | |||
) |
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
AndData | The value to AND with the PCI configuration register. |
References GetPciExpressAddress(), and MmioBitFieldAnd16().
Referenced by PciBitFieldAnd16().
UINT32 EFIAPI PciExpressBitFieldAnd32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | AndData | |||
) |
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
AndData | The value to AND with the PCI configuration register. |
References GetPciExpressAddress(), and MmioBitFieldAnd32().
Referenced by PciBitFieldAnd32().
UINT8 EFIAPI PciExpressBitFieldAnd8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | AndData | |||
) |
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
AndData | The value to AND with the PCI configuration register. |
References GetPciExpressAddress(), and MmioBitFieldAnd8().
Referenced by PciBitFieldAnd8().
UINT16 EFIAPI PciExpressBitFieldAndThenOr16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | AndData, | |||
IN UINT16 | OrData | |||
) |
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References GetPciExpressAddress(), and MmioBitFieldAndThenOr16().
Referenced by PciBitFieldAndThenOr16().
UINT32 EFIAPI PciExpressBitFieldAndThenOr32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | AndData, | |||
IN UINT32 | OrData | |||
) |
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References GetPciExpressAddress(), and MmioBitFieldAndThenOr32().
Referenced by PciBitFieldAndThenOr32().
UINT8 EFIAPI PciExpressBitFieldAndThenOr8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | AndData, | |||
IN UINT8 | OrData | |||
) |
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
AndData | The value to AND with the PCI configuration register. | |
OrData | The value to OR with the result of the AND operation. |
References GetPciExpressAddress(), and MmioBitFieldAndThenOr8().
Referenced by PciBitFieldAndThenOr8().
UINT16 EFIAPI PciExpressBitFieldOr16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | OrData | |||
) |
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
OrData | The value to OR with the PCI configuration register. |
References GetPciExpressAddress(), and MmioBitFieldOr16().
Referenced by PciBitFieldOr16().
UINT32 EFIAPI PciExpressBitFieldOr32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | OrData | |||
) |
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
OrData | The value to OR with the PCI configuration register. |
References GetPciExpressAddress(), and MmioBitFieldOr32().
Referenced by PciBitFieldOr32().
UINT8 EFIAPI PciExpressBitFieldOr8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | OrData | |||
) |
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
OrData | The value to OR with the PCI configuration register. |
References GetPciExpressAddress(), and MmioBitFieldOr8().
Referenced by PciBitFieldOr8().
Reads a bit field of a PCI configuration register.
Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | The PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. |
References GetPciExpressAddress(), and MmioBitFieldRead16().
Referenced by PciBitFieldRead16().
Reads a bit field of a PCI configuration register.
Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | The PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. |
References GetPciExpressAddress(), and MmioBitFieldRead32().
Referenced by PciBitFieldRead32().
Reads a bit field of a PCI configuration register.
Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().
Address | The PCI configuration register to read. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. |
References GetPciExpressAddress(), and MmioBitFieldRead8().
Referenced by PciBitFieldRead8().
UINT16 EFIAPI PciExpressBitFieldWrite16 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT16 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..15. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..15. | |
Value | The new value of the bit field. |
References GetPciExpressAddress(), and MmioBitFieldWrite16().
Referenced by PciBitFieldWrite16().
UINT32 EFIAPI PciExpressBitFieldWrite32 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT32 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..31. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..31. | |
Value | The new value of the bit field. |
References GetPciExpressAddress(), and MmioBitFieldWrite32().
Referenced by PciBitFieldWrite32().
UINT8 EFIAPI PciExpressBitFieldWrite8 | ( | IN UINTN | Address, | |
IN UINTN | StartBit, | |||
IN UINTN | EndBit, | |||
IN UINT8 | Value | |||
) |
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.
If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
Address | The PCI configuration register to write. | |
StartBit | The ordinal of the least significant bit in the bit field. Range 0..7. | |
EndBit | The ordinal of the most significant bit in the bit field. Range 0..7. | |
Value | The new value of the bit field. |
References GetPciExpressAddress(), and MmioBitFieldWrite8().
Referenced by PciBitFieldWrite8().
Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
OrData | The value to OR with the PCI configuration register. |
References GetPciExpressAddress(), and MmioOr16().
Referenced by PciOr16().
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
OrData | The value to OR with the PCI configuration register. |
References GetPciExpressAddress(), and MmioOr32().
Referenced by PciOr32().
Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
OrData | The value to OR with the PCI configuration register. |
References GetPciExpressAddress(), and MmioOr8().
Referenced by PciOr8().
Reads a 16-bit PCI configuration register.
Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. |
References GetPciExpressAddress(), and MmioRead16().
Referenced by PciExpressReadBuffer(), and PciRead16().
Reads a 32-bit PCI configuration register.
Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. |
References GetPciExpressAddress(), and MmioRead32().
Referenced by PciExpressReadBuffer(), and PciRead32().
Reads an 8-bit PCI configuration register.
Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. |
References GetPciExpressAddress(), and MmioRead8().
Referenced by PciExpressReadBuffer(), and PciRead8().
UINTN EFIAPI PciExpressReadBuffer | ( | IN UINTN | StartAddress, | |
IN UINTN | Size, | |||
OUT VOID * | Buffer | |||
) |
Reads a range of PCI configuration registers into a caller supplied buffer.
Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.
If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
StartAddress | The starting address that encodes the PCI Bus, Device, Function and Register. | |
Size | The size in bytes of the transfer. | |
Buffer | The pointer to a buffer receiving the data read. |
References ASSERT, NULL, PciExpressRead16(), PciExpressRead32(), PciExpressRead8(), WriteUnaligned16(), and WriteUnaligned32().
Referenced by PciReadBuffer().
RETURN_STATUS EFIAPI PciExpressRegisterForRuntimeAccess | ( | IN UINTN | Address | ) |
Registers a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap().
Registers the PCI device specified by Address so all the PCI configuration registers associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
If Address > 0x0FFFFFFF, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. |
RETURN_SUCCESS | The PCI device was registered for runtime access. | |
RETURN_UNSUPPORTED | An attempt was made to call this function after ExitBootServices(). | |
RETURN_UNSUPPORTED | The resources required to access the PCI device at runtime could not be mapped. | |
RETURN_OUT_OF_RESOURCES | There are not enough resources available to complete the registration. |
References ASSERT, EFI_GCD_MEMORY_SPACE_DESCRIPTOR::Attributes, EFI_ERROR, EFI_MEMORY_RUNTIME, EfiAtRuntime(), gDS, DXE_SERVICES::GetMemorySpaceDescriptor, GetPciExpressAddress(), mDxeRuntimePciExpressLibNumberOfRuntimeRanges, mDxeRuntimePciExpressLibRegistrationTable, NULL, ReallocateRuntimePool(), RETURN_OUT_OF_RESOURCES, RETURN_SUCCESS, RETURN_UNSUPPORTED, DXE_SERVICES::SetMemorySpaceAttributes, and VOID.
Referenced by PciRegisterForRuntimeAccess().
Writes a 16-bit PCI configuration register.
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
Value | The value to write. |
References GetPciExpressAddress(), and MmioWrite16().
Referenced by PciExpressWriteBuffer(), and PciWrite16().
Writes a 32-bit PCI configuration register.
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
Value | The value to write. |
References GetPciExpressAddress(), and MmioWrite32().
Referenced by PciExpressWriteBuffer(), and PciWrite32().
Writes an 8-bit PCI configuration register.
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
Address | The address that encodes the PCI Bus, Device, Function and Register. | |
Value | The value to write. |
References GetPciExpressAddress(), and MmioWrite8().
Referenced by PciExpressWriteBuffer(), and PciWrite8().
UINTN EFIAPI PciExpressWriteBuffer | ( | IN UINTN | StartAddress, | |
IN UINTN | Size, | |||
IN VOID * | Buffer | |||
) |
Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.
If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().
StartAddress | The starting address that encodes the PCI Bus, Device, Function and Register. | |
Size | The size in bytes of the transfer. | |
Buffer | The pointer to a buffer containing the data to write. |
References ASSERT, NULL, PciExpressWrite16(), PciExpressWrite32(), PciExpressWrite8(), ReadUnaligned16(), and ReadUnaligned32().
Referenced by PciWriteBuffer().
UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0 |
The table index of the most recent virtual address lookup.
Referenced by GetPciExpressAddress().
The number of PCI devices that have been registered for runtime access.
Referenced by DxeRuntimePciExpressLibVirtualNotify(), GetPciExpressAddress(), and PciExpressRegisterForRuntimeAccess().
Module global that contains the base physical address of the PCI Express MMIO range.
Referenced by DxeRuntimePciExpressLibConstructor(), and GetPciExpressAddress().
PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE* mDxeRuntimePciExpressLibRegistrationTable = NULL |
The table of PCI devices that have been registered for runtime access.
Referenced by DxeRuntimePciExpressLibDestructor(), DxeRuntimePciExpressLibVirtualNotify(), GetPciExpressAddress(), and PciExpressRegisterForRuntimeAccess().
Set Virtual Address Map Event
Referenced by DxeRuntimePciExpressLibConstructor(), and DxeRuntimePciExpressLibDestructor().