Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0 |
#define PAL_APPLICATION_REGISTER_READABLE 1 |
#define PAL_BRAND_INFO 274 |
PAL Procedure - PAL_BRAND_INFO.
Provides processor branding information. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at physical and Virtual mode.
Index | Index of PAL_BRAND_INFO within the list of PAL procedures. | |
InfoRequest | Unsigned 64-bit integer specifying the information that is being requested. (See PAL_BRAND_INFO_ID_REQUEST) | |
Address | Unsigned 64-bit integer specifying the address of the 128-byte block to which the processor brand string shall be written. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-6 | Input argument is not implemented. |
#define PAL_BRAND_INFO_ID_REQUEST 0 |
The ASCII brand identification string will be copied to the address specified in the address input argument. The processor brand identification string is defined to be a maximum of 128 characters long; 127 bytes will contain characters and the 128th byte is defined to be NULL (0). A processor may return less than the 127 ASCII characters as long as the string is null terminated. The string length will be placed in the brand_info return argument.
#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57 |
When 0, BERR# is signalled when internal processor requestor initiated bus errors are detected. When 1, internal requester bus errors are not signalled on the bus.
#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61 |
When 0, bus errors are detected, single bit errors are corrected., and a CMCI or MCA is generated internally to the processor. When 1, no bus address errors are detected or corrected.
#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62 |
When 0, bus address errors are signalled on the bus. When 1, no bus errors are signalled on the bus. If Disable Bus Address Error Checking is 1, this bit is ignored.
#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63 |
When 0, bus data errors are detected and single bit errors are corrected. When 1, no error detection or correction is done.
#define PAL_BUS_DISABLE_ERROR_CHECK BIT56 |
When 0, the processor takes an MCA if BERR# is asserted. When 1, the processor ignores the BERR# signal.
#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58 |
When 0, BERR# is signalled if a bus error is detected. When 1, bus errors are not signalled on the bus.
#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59 |
When 0, bus protocol errors (BINIT#) are detected and sampled and an MCA is generated internally to the processor. When 1, the processor will ignore bus protocol error conditions (BINIT#).
#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60 |
When 0, bus protocol errors (BINIT#) are signaled by the processor on the bus. When 1, bus protocol errors (BINIT#) are not signaled on the bus. If Disable Bus Initialization Event Checking is 1, this bit is ignored.
#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55 |
When 0, the processor asserts BINIT# if it detects a parity error on the signals which identify the transactions to which this is a response. When 1, the processor ignores parity on these signals.
#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54 |
When 0, the in-order transaction queue is limited only by the number of hardware entries. When 1, the processor's in-order transactions queue is limited to one entry.
#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53 |
Enable a bus cache line replacement transaction when a cache line in the exclusive state is replaced from the highest level processor cache and is not present in the lower level processor caches. When 0, no bus cache line replacement transaction will be seen on the bus. When 1, bus cache line replacement transactions will be seen on the bus when the above condition is detected.
#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30 |
When 0, the data bus is configured at the 2x data transfer rate.When 1, the data bus is configured at the 1x data transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the processor executes locked transactions atomically. When 1, the processor masks the bus lock signal and executes locked transactions as a non-atomic series of transactions.
#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52 |
Enable a bus cache line replacement transaction when a cache line in the shared or exclusive state is replaced from the highest level processor cache and is not present in the lower level processor caches. When 0, no bus cache line replacement transaction will be seen on the bus. When 1, bus cache line replacement transactions will be seen on the bus when the above condition is detected.
#define PAL_BUS_GET_FEATURES 9 |
PAL Procedure - PAL_BUS_GET_FEATURES.
Return configurable processor bus interface features and their current settings. It is required by Itanium processors. The PAL procedure supports the Stacked Register calling convention. It could be called at physical mode.
Index | Index of PAL_BUS_GET_FEATURES within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 64-bit vector of current feature settings.
R11 64-bit vector of features controllable by software. (1=controllable, 0= not controllable)
#define PAL_BUS_REQUEST_BUS_PARKING BIT29 |
When 0, the processor will deassert bus request when finished with each transaction. When 1, the processor will continue to assert bus request after it has finished, if it was the last agent to own the bus and if there are no other pending requests.
#define PAL_BUS_SET_FEATURES 10 |
PAL Procedure - PAL_BUS_SET_FEATURES.
Enable or disable configurable features in processor bus interface. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_BUS_SET_FEATURES within the list of PAL procedures. | |
FeatureSelect | 64-bit vector denoting desired state of each feature (1=select, 0=non-select). |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_CACHE_ATTR_WB 1 |
#define PAL_CACHE_ATTR_WT 0 |
Attributes of PAL_CACHE_CONFIG_INFO1
#define PAL_CACHE_FLUSH 1 |
PAL Procedure - PAL_CACHE_FLUSH.
Flush the instruction or data caches. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at virtual mode and physical mode.
Index | Index of PAL_CACHE_FLUSH within the list of PAL procedures. | |
CacheType | Unsigned 64-bit integer indicating which cache to flush. | |
Operation | Formatted bit vector indicating the operation of this call. | |
ProgressIndicator | Unsigned 64-bit integer specifying the starting position of the flush operation. |
2 | Call completed without error, but a PMI was taken during the execution of this procedure. | |
1 | Call has not completed flushing due to a pending interrupt. | |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error |
R10 Unsigned 64-bit integer specifying the starting position of the flush operation.
R11 Unsigned 64-bit integer specifying the vector number of the pending interrupt.
Referenced by InvalidateInstructionCache(), WriteBackDataCache(), and WriteBackInvalidateDataCache().
#define PAL_CACHE_FLUSH_ALL 3 |
#define PAL_CACHE_FLUSH_DATA_ALL 2 |
Referenced by WriteBackDataCache(), and WriteBackInvalidateDataCache().
#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1 |
CacheType of PAL_CACHE_FLUSH.
Referenced by InvalidateInstructionCache().
#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0 |
Bitmask of Opearation of PAL_CACHE_FLUSH.
Referenced by InvalidateInstructionCache(), and WriteBackInvalidateDataCache().
#define PAL_CACHE_FLUSH_NO_INTERRUPT 0 |
Referenced by InvalidateInstructionCache(), WriteBackDataCache(), and WriteBackInvalidateDataCache().
#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0 |
Referenced by WriteBackDataCache().
#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1 |
#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4 |
#define PAL_CACHE_INFO 2 |
PAL Procedure - PAL_CACHE_INFO.
Return detailed instruction or data cache information. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at virtual mode and physical mode.
Index | Index of PAL_CACHE_INFO within the list of PAL procedures. | |
CacheLevel | Unsigned 64-bit integer specifying the level in the cache hierarchy for which information is requested. This value must be between 0 and one less than the value returned in the cache_levels return value from PAL_CACHE_SUMMARY. | |
CacheType | Unsigned 64-bit integer with a value of 1 for instruction cache and 2 for data or unified cache. All other values are reserved. | |
Reserved | Should be 0. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error |
R10 Detail the characteristics of a given processor controlled cache in the cache hierarchy. See PAL_CACHE_INFO_RETURN2.
R11 Reserved with 0.
#define PAL_CACHE_INIT 3 |
PAL Procedure - PAL_CACHE_INIT.
Initialize the instruction or data caches. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_CACHE_INIT within the list of PAL procedures. | |
Level | Unsigned 64-bit integer containing the level of cache to initialize. If the cache level can be initialized independently, only that level will be initialized. Otherwise implementation-dependent side-effects will occur. | |
CacheType | Unsigned 64-bit integer with a value of 1 to initialize the instruction cache, 2 to initialize the data cache, or 3 to initialize both. All other values are reserved. | |
Restrict | Unsigned 64-bit integer with a value of 0 or 1. All other values are reserved. If restrict is 1 and initializing the specified level and cache_type of the cache would cause side-effects, PAL_CACHE_INIT will return -4 instead of initializing the cache. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-4 | Call could not initialize the specified level and cache_type of the cache without side-effects and restrict was 1. |
#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL |
Level of PAL_CACHE_INIT.
#define PAL_CACHE_INIT_NO_RESTRICT 0 |
Restrict of PAL_CACHE_INIT.
#define PAL_CACHE_INIT_RESTRICTED 1 |
#define PAL_CACHE_INIT_TYPE_DATA 0x2 |
#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1 |
CacheType
#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3 |
#define PAL_CACHE_LINE_INIT 31 |
PAL Procedure - PAL_CACHE_LINE_INIT.
Initialize tags and data of a cache line for processor testing. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical and virtual mode.
Index | Index of PAL_CACHE_LINE_INIT within the list of PAL procedures. | |
Address | Unsigned 64-bit integer value denoting the physical address from which the physical page number is to be generated. The address must be an implemented physical address, bit 63 must be zero. | |
DataValue | 64-bit data value which is used to initialize the cache line. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1 |
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3 |
#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0 |
PAL_CACHE_CONFIG_INFO1.StoreHint
#define PAL_CACHE_PROT_INFO 38 |
PAL Procedure - PAL_CACHE_PROT_INFO.
Return instruction or data cache protection information. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_CACHE_PROT_INFO within the list of PAL procedures. | |
CacheLevel | Unsigned 64-bit integer specifying the level in the cache hierarchy for which information is requested. This value must be between 0 and one less than the value returned in the cache_levels return value from PAL_CACHE_SUMMARY. | |
CacheType | Unsigned 64-bit integer with a value of 1 for instruction cache and 2 for data or unified cache. All other values are reserved. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Detail the characteristics of a given processor controlled cache in the cache hierarchy. See PAL_CACHE_PROTECTION[2..3].
R11 Detail the characteristics of a given processor controlled cache in the cache hierarchy. See PAL_CACHE_PROTECTION[4..5].
#define PAL_CACHE_PROTECTION_ECC_PROTECT 3 |
#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2 |
#define PAL_CACHE_PROTECTION_NONE_PROTECT 0 |
#define PAL_CACHE_PROTECTION_ODD_PROTECT 1 |
#define PAL_CACHE_PROTECTION_PROTECT_DATA 0 |
#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3 |
#define PAL_CACHE_PROTECTION_PROTECT_TAG 1 |
#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2 |
#define PAL_CACHE_READ 259 |
PAL Procedure - PAL_CACHE_READ.
Read tag and data of a cache line for diagnostic testing. It is optional. The PAL procedure supports the Satcked Registers calling convention. It could be called at physical mode.
Index | Index of PAL_CACHE_READ within the list of PAL procedures. | |
LineId | 8-byte formatted value describing where in the cache to read the data. | |
Address | 64-bit 8-byte aligned physical address from which to read the data. The address must be an implemented physical address on the processor model with bit 63 set to zero. |
1 | The word at address was found in the cache, but the line was invalid. | |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-5 | The word at address was not found in the cache. | |
-7 | The operation requested is not supported for this cache_type and level. |
R10 The number of bits returned in data.
R11 The status of the cache line.
#define PAL_CACHE_SHARED_INFO 43 |
PAL Procedure - PAL_CACHE_SHARED_INFO.
Returns information on which logical processors share caches. It is optional. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_CACHE_SHARED_INFO within the list of PAL procedures. | |
CacheLevel | Unsigned 64-bit integer specifying the level in the cache hierarchy for which information is requested. This value must be between 0 and one less than the value returned in the cache_levels return value from PAL_CACHE_SUMMARY. | |
CacheType | Unsigned 64-bit integer with a value of 1 for instruction cache and 2 for data or unified cache. All other values are reserved. | |
ProcNumber | Unsigned 64-bit integer that specifies for which logical processor information is being requested. This input argument must be zero for the first call to this procedure and can be a maximum value of one less than the number of logical processors sharing this cache, which is returned by the num_shared return value. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 The format of PAL_PCOC_N_CACHE_INFO1.
R11 The format of PAL_PCOC_N_CACHE_INFO2.
#define PAL_CACHE_STORE_NONE_TEMPORAL 3 |
#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3 |
#define PAL_CACHE_STORE_TEMPORAL 0 |
PAL_CACHE_CONFIG_INFO1.StoreHint
#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0 |
PAL_CACHE_CONFIG_INFO1.StoreHint
#define PAL_CACHE_SUMMARY 4 |
PAL Procedure - PAL_CACHE_SUMMARY.
Return a summary of the cache hierarchy. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_CACHE_SUMMARY within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 UniqueCaches Unsigned 64-bit integer denoting the number of unique caches implemented by the processor. This has a maximum of 2*cache_levels, but may be less if any of the levels in the cache hierarchy are unified caches or do not have both instruction and data caches.
#define PAL_CACHE_WRITE 260 |
PAL Procedure - PAL_CACHE_WRITE.
Write tag and data of a cache for diagnostic testing. It is optional. The PAL procedure supports the Satcked Registers calling convention. It could be called at physical mode.
Index | Index of PAL_CACHE_WRITE within the list of PAL procedures. | |
LineId | 8-byte formatted value describing where in the cache to write the data. | |
Address | 64-bit 8-byte aligned physical address at which the data should be written. The address must be an implemented physical address on the processor model with bit 63 set to 0. | |
Data | Unsigned 64-bit integer value to write into the specified part of the cache. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-7 | The operation requested is not supported for this cache_type and level. |
#define PAL_CONTROL_REGISTER_IMPLEMENTED 2 |
#define PAL_CONTROL_REGISTER_READABLE 3 |
#define PAL_COPY_INFO 30 |
PAL Procedure - PAL_COPY_INFO.
Return information needed to relocate PAL procedures and PAL PMI code to memory. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_COPY_INFO within the list of PAL procedures. | |
CopyType | Unsigned integer denoting type of procedures for which copy information is requested. | |
PlatformInfo | 8-byte formatted value describing the number of processors and the number of interrupt controllers currently enabled on the system. See PAL_PLATFORM_INFO. | |
McaProcStateInfo | Unsigned integer denoting the number of bytes that SAL needs for the min-state save area for each processor. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Unsigned integer denoting the starting alignment of the data to be copied.
#define PAL_COPY_PAL 256 |
PAL Procedure - PAL_COPY_PAL.
Relocate PAL procedures and PAL PMI code to memory. It is required by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at physical mode.
Index | Index of PAL_COPY_PAL within the list of PAL procedures. | |
TargetAddress | Physical address of a memory buffer to copy relocatable PAL procedures and PAL PMI code. | |
AllocSize | Unsigned integer denoting the size of the buffer passed by SAL for the copy operation. | |
CopyOption | Unsigned integer indicating whether relocatable PAL code and PAL PMI code should be copied from firmware address space to main memory. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_DEBUG_INFO 11 |
PAL Procedure - PAL_DEBUG_INFO.
Return the number of instruction and data breakpoint registers. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_DEBUG_INFO within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Unsigned 64-bit integer denoting the number of pairs of data debug registers implemented by the processor.
#define PAL_ENTER_IA_32_ENV 33 |
PAL Procedure - PAL_ENTER_IA_32_ENV.
Enter IA-32 System environment. It is optional. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Note: Since this is a special call, it does not follow the PAL static register calling convention. GR28 contains the index of PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other input arguments including GR29-GR31 are setup by SAL to values as required by the IA-32 operating system defined in Table 11-67. The registers that are designated as preserved, scratch, input arguments and procedure return values by the static procedure calling convention are not followed by this call. For instance, GR5 and GR6 need not be preserved since these are regarded as scratch by the IA-32 operating system. Note: In an MP system, this call must be COMPLETED on the first CPU to enter the IA-32 System Environment (may or may not be the BSP) prior to being called on the remaining processors in the MP system.
Index | GR28 contains the index of the PAL_ENTER_IA_32_ENV call within the list of PAL procedures. |
The | status is returned in GR4. -1 - Un-implemented procedure 0 JMPE detected at privilege level |
2 - IA-32 Firmware Checksum Error
3 - SAL allocated buffer for IA-32 System Environment operation is not properly aligned
4 - Error in SAL MP Info Table
5 - Error in SAL Memory Descriptor Table
6 - Error in SAL System Table
7 - Inconsistent IA-32 state
8 - IA-32 Firmware Internal Error
9 - IA-32 Soft Reset (Note: remaining register state is undefined for this termination reason)
10 - Machine Check Error
11 - Error in SAL I/O Intercept Table
12 - Processor exit due to other processor in MP system terminating the IA32 system environment. (Note: remaining register state is undefined for this termination reason.)
13 - Itanium architecture-based state corruption by either SAL PMI handler or I/O Intercept callback function.
#define PAL_ERR_INFO_BY_LEVEL_INDEX 0 |
#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4 |
#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3 |
#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2 |
#define PAL_ERR_INFO_TARGET_ADDRESS 1 |
#define PAL_FIXED_ADDR 12 |
PAL Procedure - PAL_FIXED_ADDR.
Return the fixed component of a processor's directed address. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_FIXED_ADDR within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_FREQ_BASE 13 |
PAL Procedure - PAL_FREQ_BASE.
Return the frequency of the output clock for use by the platform, if generated by the processor. It is optinal. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_FREQ_BASE within the list of PAL procedures. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. |
Referenced by GetPerformanceCounterProperties().
#define PAL_FREQ_RATIOS 14 |
PAL Procedure - PAL_FREQ_RATIOS.
Return ratio of processor, bus, and interval time counter to processor input clock or output clock for platform use, if generated by the processor. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_FREQ_RATIOS within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Ratio of the bus frequency to the input clock of the processor, if the platform clock is generated externally or to the output clock to the platform, if the platform clock is generated by the processor.
R11 Ratio of the interval timer counter rate to input clock of the processor, if the platform clock is generated externally or to the output clock to the platform, if the platform clock is generated by the processor.
Referenced by GetPerformanceCounterProperties().
#define PAL_GET_HW_POLICY 48 |
PAL Procedure - PAL_GET_HW_POLICY.
Returns the current hardware resource sharing policy of the processor. It is optional by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical and Virtual mode.
Index | Index of PAL_GET_HW_POLICY within the list of PAL procedures. | |
ProcessorNumber | Unsigned 64-bit integer that specifies for which logical processor information is being requested. This input argument must be zero for the first call to this procedure and can be a maximum value of one less than the number of logical processors impacted by the hardware resource sharing policy, which is returned by the R10 return value. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
R10 Unsigned 64-bit integer that returns the number of logical processors impacted by the policy input argument.
R11 Unsigned 64-bit integer containing the logical address of one of the logical processors impacted by policy modification.
#define PAL_GET_PSTATE 262 |
PAL Procedure - PAL_GET_PSTATE.
Returns the performance index of the processor. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at physical and Virtual mode.
Index | Index of PAL_GET_PSTATE within the list of PAL procedures. | |
Type | Type of performance_index value to be returned by this procedure.See PAL_GET_PSTATE.Type above. |
1 | Call completed without error, but accuracy of performance index has been impacted by a thermal throttling event, or a hardware-initiated event. | |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_GET_PSTATE_AVERAGE 2 |
#define PAL_GET_PSTATE_AVERAGE_NEW_START 1 |
#define PAL_GET_PSTATE_NOW 3 |
#define PAL_GET_PSTATE_RECENT 0 |
#define PAL_HALT 28 |
PAL Procedure - PAL_HALT.
Enter the low-power HALT state or an implementation-dependent low-power state. It is optinal. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_HALT within the list of PAL procedures. | |
HaltState | Unsigned 64-bit integer denoting low power state requested. | |
IoDetailPtr | 8-byte aligned physical address pointer to information on the type of I/O (load/store) requested. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_HALT_INFO 257 |
PAL Procedure - PAL_HALT_INFO.
Return the low power capabilities of the processor. It is required by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at physical and virtual mode.
Index | Index of PAL_HALT_INFO within the list of PAL procedures. | |
PowerBuffer | 64-bit pointer to a 64-byte buffer aligned on an 8-byte boundary. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_HALT_LIGHT 29 |
PAL Procedure - PAL_HALT_LIGHT.
Enter the low power LIGHT HALT state. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical and virtual mode.
Index | Index of PAL_HALT_LIGHT within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
Referenced by CpuSleep().
#define PAL_INIT_PENDING BIT1 |
#define PAL_LOGICAL_TO_PHYSICAL 42 |
PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
Return information on which logical processors map to a physical processor die. It is optinal. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL procedures. | |
ProcessorNumber | Signed 64-bit integer that specifies for which logical processor information is being requested. When this input argument is -1, information is returned about the logical processor on which the procedure call is made. This input argument must be in the range of 1 up to one less than the number of logical processors returned by num_log in the log_overview return value. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
#define PAL_MC_CLEAR_LOG 21 |
PAL Procedure - PAL_MC_CLEAR_LOG.
Clear all error information from processor error logging registers. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_MC_CLEAR_LOG within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_MC_DRAIN 22 |
PAL Procedure - PAL_MC_DRAIN.
Ensure that all operations that could cause an MCA have completed. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_MC_DRAIN within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_MC_DYNAMIC_STATE 24 |
PAL Procedure - PAL_MC_DYNAMIC_STATE.
Return Processor Dynamic State for logging by SAL. It is optional. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_MC_DYNAMIC_STATE within the list of PAL procedures. | |
Offset | Offset of the next 8 bytes of Dynamic Processor State to return. (multiple of 8). |
0 | Call completed without error | |
-1 | Unimplemented procedure. | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Next 8 bytes of Dynamic Processor State.
#define PAL_MC_ERROR_INFO 25 |
PAL Procedure - PAL_MC_ERROR_INFO.
Return Processor Machine Check Information and Processor Static State for logging by SAL. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical and virtual mode.
Index | Index of PAL_MC_ERROR_INFO within the list of PAL procedures. | |
InfoIndex | Unsigned 64-bit integer identifying the error information that is being requested. See PAL_MC_ERROR_INFO.InfoIndex. | |
LevelIndex | 8-byte formatted value identifying the structure to return error information on. See PAL_MC_ERROR_INFO_LEVEL_INDEX. | |
ErrorTypeIndex | Unsigned 64-bit integer denoting the type of error information that is being requested for the structure identified in LevelIndex. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-6 | Argument was valid, but no error information was available |
R10 If this value is zero, all the error information specified by err_type_index has been returned. If this value is one, more structure-specific error information is available and the caller needs to make this procedure call again with level_index unchanged and err_type_index, incremented.
#define PAL_MC_ERROR_INJECT 276 |
PAL Procedure - PAL_MC_ERROR_INJECT.
Injects the requested processor error or returns information on the supported injection capabilities for this particular processor implementation. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at physical and Virtual mode.
Index | Index of PAL_MC_ERROR_INJECT within the list of PAL procedures. | |
ErrorTypeInfo | Unsigned 64-bit integer specifying the first level error information which identifies the error structure and corresponding structure hierarchy, and the error severity. | |
ErrorStructInfo | Unsigned 64-bit integer identifying the optional structure specific information that provides the second level details for the requested error. | |
ErrorDataBuffer | 64-bit physical address of a buffer providing additional parameters for the requested error. The address of this buffer must be 8-byte aligned. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-4 | Call completed with error; the requested error could not be injected due to failure in locating the target location in the specified structure. | |
-5 | Argument was valid, but requested error injection capability is not supported. | |
-9 | Call requires PAL memory buffer. |
R10 64-bit vector specifying the architectural resources that are used by the procedure.
#define PAL_MC_EXPECTED 23 |
PAL Procedure - PAL_MC_EXPECTED.
Set/Reset Expected Machine Check Indicator. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_MC_EXPECTED within the list of PAL procedures. | |
Expected | Unsigned integer with a value of 0 or 1 to set or reset the hardware resource PALE_CHECK examines for expected machine checks. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_MC_PENDING BIT0 |
#define PAL_MC_REGISTER_MEM 27 |
PAL Procedure - PAL_MC_REGISTER_MEM.
Register min-state save area with PAL for machine checks and inits. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_MC_REGISTER_MEM within the list of PAL procedures. | |
Address | Physical address of the buffer to be registered with PAL. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_MC_RESUME 26 |
PAL Procedure - PAL_MC_RESUME.
Restore minimal architected state and return to interrupted process. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_MC_RESUME within the list of PAL procedures. | |
SetCmci | Unsigned 64 bit integer denoting whether to set the CMC interrupt. A value of 0 indicates not to set the interrupt, a value of 1 indicated to set the interrupt, and all other values are reserved. | |
SavePtr | Physical address of min-state save area used to used to restore processor state. | |
NewContext | Unsigned 64-bit integer denoting whether the caller is returning to a new context. A value of 0 indicates the caller is returning to the interrupted context, a value of 1 indicates that the caller is returning to a new context. |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_MEM_ATTRIB 5 |
PAL Procedure - PAL_MEM_ATTRIB.
Return a list of supported memory attributes.. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_MEM_ATTRIB within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_MEMORY_ATTR_NATPAGE 7 |
#define PAL_MEMORY_ATTR_UC 4 |
#define PAL_MEMORY_ATTR_UCE 5 |
#define PAL_MEMORY_ATTR_WB 0 |
#define PAL_MEMORY_ATTR_WC 6 |
#define PAL_MEMORY_BUFFER 277 |
PAL Procedure - PAL_MEMORY_BUFFER.
Provides cacheable memory to PAL for exclusive use during runtime. It is optional by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_MEMORY_BUFFER within the list of PAL procedures. | |
BaseAddress | Physical address of the memory buffer allocated for PAL use. | |
AllocSize | Unsigned integer denoting the size of the memory buffer. | |
ControlWord | Formatted bit vector that provides control options for this procedure. See PAL_MEMORY_CONTROL_WORD above. |
1 | Call has not completed a buffer relocation due to a pending interrupt | |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_PERF_MON_INFO 15 |
PAL Procedure - PAL_PERF_MON_INFO.
Return the number and type of performance monitors. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_PERF_MON_INFO within the list of PAL procedures. | |
PerformanceBuffer | An address to an 8-byte aligned 128-byte memory buffer. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_PLATFORM_ADDR 16 |
PAL Procedure - PAL_PLATFORM_ADDR.
Specify processor interrupt block address and I/O port space address. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_PLATFORM_ADDR within the list of PAL procedures. | |
Type | Unsigned 64-bit integer specifying the type of block. 0 indicates that the processor interrupt block pointer should be initialized. 1 indicates that the processor I/O block pointer should be initialized. | |
Address | Unsigned 64-bit integer specifying the address to which the processor I/O block or interrupt block shall be set. The address must specify an implemented physical address on the processor model, bit 63 is ignored. |
0 | Call completed without error | |
-1 | Unimplemented procedure. | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0 |
#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1 |
#define PAL_PMI_ENTRYPOINT 32 |
PAL Procedure - PAL_PMI_ENTRYPOINT.
Register PMI memory entrypoints with processor. It is required by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at physical mode.
Index | Index of PAL_PMI_ENTRYPOINT within the list of PAL procedures. | |
SalPmiEntry | 256-byte aligned physical address of SAL PMI entrypoint in memory. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_PREFETCH_VISIBILITY 41 |
PAL Procedure - PAL_PREFETCH_VISIBILITY.
Used in architected sequence to transition pages from a cacheable, speculative attribute to an uncacheable attribute. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_PREFETCH_VISIBILITY within the list of PAL procedures. | |
TransitionType | Unsigned integer specifying the type of memory attribute transition that is being performed. |
1 | Call completed without error; this call is not necessary on remote processors. | |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_PROC_GET_FEATURES 17 |
PAL Procedure - PAL_PROC_GET_FEATURES.
Return configurable processor features and their current setting. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_PROC_GET_FEATURES within the list of PAL procedures. | |
Reserved | Reserved parameter. | |
FeatureSet | Feature set information is being requested for. |
1 | Call completed without error; The feature_set passed is not supported but a feature_set of a larger value is supported. | |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-8 | feature_set passed is beyond the maximum feature_set supported |
R10 64-bit vector of current feature settings. See PAL_PROCESSOR_FEATURES.
R11 64-bit vector of features controllable by software.
#define PAL_PROC_SET_FEATURES 18 |
PAL Procedure - PAL_PROC_SET_FEATURES.
Enable or disable configurable processor features. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_PROC_SET_FEATURES within the list of PAL procedures. | |
FeatureSelect | 64-bit vector denoting desired state of each feature (1=select, 0=non-select). | |
FeatureSet | Feature set to apply changes to. See PAL_PROC_GET_FEATURES for more information on feature sets. |
1 | Call completed without error; The feature_set passed is not supported but a feature_set of a larger value is supported | |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-8 | feature_set passed is beyond the maximum feature_set supported |
#define PAL_PROCESSOR_ERROR_MAP 0 |
#define PAL_PROCESSOR_STATE_PARAM 1 |
#define PAL_PSTATE_INFO 44 |
PAL Procedure - PAL_PSTATE_INFO.
Returns information about the P-states supported by the processor. It is optional by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical and Virtual mode.
Index | Index of PAL_PSTATE_INFO within the list of PAL procedures. | |
PStateBuffer | 64-bit pointer to a 256-byte buffer aligned on an 8-byte boundary. See PAL_PSTATE_INFO_BUFFER above. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Dependency domain information
#define PAL_PTCE_INFO 6 |
PAL Procedure - PAL_PTCE_INFO.
Return information needed for ptc.e instruction to purge entire TC. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_PTCE_INFO within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Two unsigned 32-bit integers denoting the loop counts of the outer (loop 1) and inner (loop 2) purge loops. count1 (loop 1) is contained in bits 63:32 of the parameter, and count2 (loop 2) is contained in bits 31:0 of the parameter.
R11 Two unsigned 32-bit integers denoting the loop strides of the outer (loop 1) and inner (loop 2) purge loops. stride1 (loop 1) is contained in bits 63:32 of the parameter, and stride2 (loop 2) is contained in bits 31:0 of the parameter.
#define PAL_REGISTER_INFO 39 |
PAL Procedure - PAL_REGISTER_INFO.
Return AR and CR register information. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_REGISTER_INFO within the list of PAL procedures. | |
InfoRequest | Unsigned 64-bit integer denoting what register information is requested. See PAL_REGISTER_INFO.InfoRequest above. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 64-bit vector denoting information for registers 64-127. Bit 0 is register 64, bit 63 is register 127.
#define PAL_RSE_INFO 19 |
PAL Procedure - PAL_RSE_INFO.
Return RSE information. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_RSE_INFO within the list of PAL procedures. | |
InfoRequest | Unsigned 64-bit integer denoting what register information is requested. See PAL_REGISTER_INFO.InfoRequest above. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 RSE hints supported by processor.
#define PAL_SET_HW_POLICY 49 |
PAL Procedure - PAL_SET_HW_POLICY.
Sets the current hardware resource sharing policy of the processor. It is optional by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical and Virtual mode.
Index | Index of PAL_SET_HW_POLICY within the list of PAL procedures. | |
Policy | Unsigned 64-bit integer specifying the hardware resource sharing policy the caller is setting. See Value of PAL_SET_HW_POLICY.Policy above. |
1 | Call completed successfully but could not change the hardware policy since a competing logical processor is set in exclusive high priority. | |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3 |
#define PAL_SET_HW_POLICY_FAIRNESS 1 |
#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2 |
#define PAL_SET_HW_POLICY_PERFORMANCE 0 |
#define PAL_SET_PSTATE 263 |
PAL Procedure - PAL_SET_PSTATE.
To request a processor transition to a given P-state. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at physical and Virtual mode.
Index | Index of PAL_SET_PSTATE within the list of PAL procedures. | |
PState | Unsigned integer denoting the processor P-state being requested. | |
ForcePState | Unsigned integer denoting whether the P-state change should be forced for the logical processor. |
1 | Call completed without error, but transition request was not accepted | |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_SHUTDOWN 45 |
PAL Procedure - PAL_SHUTDOWN.
Put the logical processor into a low power state which can be exited only by a reset event. It is optional by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_SHUTDOWN within the list of PAL procedures. | |
NotifyPlatform | 8-byte aligned physical address pointer providing details on how to optionally notify the platform that the processor is entering a shutdown state. |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_STRUCTURE_SPECIFIC_ERROR 2 |
#define PAL_SUCCESS 0x0 |
#define PAL_TEST_INFO 37 |
PAL Procedure - PAL_TEST_INFO.
Returns alignment and size requirements needed for the memory buffer passed to the PAL_TEST_PROC procedure as well as information on self-test control words for the processor self tests. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_TEST_INFO within the list of PAL procedures. | |
TestPhase | Unsigned integer that specifies which phase of the processor self-test information is being requested on. A value of 0 indicates the phase two of the processor self-test and a value of 1 indicates phase one of the processor self-test. All other values are reserved. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 Unsigned 64-bit integer denoting the alignment required for the memory buffer.
R11 48-bit wide bit-field indicating if control of the processor self-tests is supported and which bits of the test_control field are defined for use.
#define PAL_TEST_PROC 258 |
PAL Procedure - PAL_TEST_PROC.
Perform late processor self test. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode.
Index | Index of PAL_TEST_PROC within the list of PAL procedures. | |
TestAddress | 64-bit physical address of main memory area to be used by processor self-test. The memory region passed must be cacheable, bit 63 must be zero. | |
TestInfo | Input argument specifying the size of the memory buffer passed and the phase of the processor self-test that should be run. See PAL_TEST_INFO. | |
TestParam | Input argument specifying the self-test control word and the allowable memory attributes that can be used with the memory buffer. See PAL_TEST_CONTROL. |
1 | Call completed without error, but hardware failures occurred during self-test. | |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0 |
#define PAL_TR_DIRTY_IS_VALID BIT2 |
#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3 |
#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1 |
#define PAL_VERSION 20 |
PAL Procedure - PAL_VERSION.
Return version of PAL code. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and virtual mode.
Index | Index of PAL_VERSION within the list of PAL procedures. | |
InfoRequest | Unsigned 64-bit integer denoting what register information is requested. See PAL_REGISTER_INFO.InfoRequest above. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 8-byte formatted value returning the current PAL version running on the processor. See PAL_VERSION_INFO above.
#define PAL_VM_INFO 7 |
PAL Procedure - PAL_VM_INFO.
Return detailed information about virtual memory features supported in the processor. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_VM_INFO within the list of PAL procedures. | |
TcLevel | Unsigned 64-bit integer specifying the level in the TLB hierarchy for which information is required. This value must be between 0 and one less than the value returned in the vm_info_1.num_tc_levels return value from PAL_VM_SUMMARY. | |
TcType | Unsigned 64-bit integer with a value of 1 for instruction translation cache and 2 for data or unified translation cache. All other values are reserved. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 64-bit vector containing a bit for each page size supported in the specified TC, where bit position n indicates a page size of 2**n.
#define PAL_VM_PAGE_SIZE 34 |
PAL Procedure - PAL_VM_PAGE_SIZE.
Return virtual memory TC and hardware walker page sizes supported in the processor. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_VM_PAGE_SIZE within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 64-bit vector containing a bit for each architected page size supported for TLB purge operations.
#define PAL_VM_SUMMARY 8 |
PAL Procedure - PAL_VM_SUMMARY.
Return summary information about virtual memory features supported in the processor. It is required by Itanium processors. The PAL procedure supports the Static Registers calling convention. It could be called at physical mode and Virtual mode.
Index | Index of PAL_VM_SUMMARY within the list of PAL procedures. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
R10 8-byte formatted value returning global virtual memory information. See PAL_VM_INFO2 above.
#define PAL_VM_TR_READ 261 |
PAL Procedure - PAL_VM_TR_READ.
Read contents of a translation register. It is required by Itanium processors. The PAL procedure supports the Stacked Register calling convention. It could be called at physical mode.
Index | Index of PAL_VM_TR_READ within the list of PAL procedures. | |
RegNumber | Unsigned 64-bit number denoting which TR to read. | |
TrType | Unsigned 64-bit number denoting whether to read an ITR (0) or DTR (1). All other values are reserved. | |
TrBuffer | 64-bit pointer to the 32-byte memory buffer in which translation data is returned. |
0 | Call completed without error | |
-2 | Invalid argument | |
-3 | Call completed with error. |
#define PAL_VP_CREATE 265 |
PAL Procedure - PAL_VP_CREATE.
Initializes a new vpd for the operation of a new virtual processor in the virtual environment. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_CREATE within the list of PAL procedures. | |
Vpd | 64-bit host virtual pointer to the Virtual Processor Descriptor (VPD). | |
HostIva | 64-bit host virtual pointer to the host IVT for the virtual processor | |
OptionalHandler | 64-bit non-zero host-virtual pointer to an optional handler for virtualization intercepts. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_VP_ENV_INFO 266 |
PAL Procedure - PAL_VP_ENV_INFO.
Returns the parameters needed to enter a virtual environment. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_ENV_INFO within the list of PAL procedures. | |
Vpd | 64-bit host virtual pointer to the Virtual Processor Descriptor (VPD). | |
HostIva | 64-bit host virtual pointer to the host IVT for the virtual processor | |
OptionalHandler | 64-bit non-zero host-virtual pointer to an optional handler for virtualization intercepts. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
R10 64-bit vector of virtual environment information. See PAL_VP_ENV_INFO_RETURN.
#define PAL_VP_EXIT_ENV 267 |
PAL Procedure - PAL_VP_EXIT_ENV.
Allows a logical processor to exit a virtual environment. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_EXIT_ENV within the list of PAL procedures. | |
Iva | Optional 64-bit host virtual pointer to the IVT when this procedure is done |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_VP_INIT_ENV 268 |
PAL Procedure - PAL_VP_INIT_ENV.
Allows a logical processor to enter a virtual environment. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_INIT_ENV within the list of PAL procedures. | |
ConfigOptions | 64-bit vector of global configuration settings. | |
PhysicalBase | Host physical base address of a block of contiguous physical memory for the PAL virtual environment buffer 1) This memory area must be allocated by the VMM and be 4K aligned. The first logical processor to enter the environment will initialize the physical block for virtualization operations. | |
VirtualBase | Host virtual base address of the corresponding physical memory block for the PAL virtual environment buffer : The VMM must maintain the host virtual to host physical data and instruction translations in TRs for addresses within the allocated address space. Logical processors in this virtual environment will use this address when transitioning to virtual mode operations. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_VP_REGISTER 269 |
PAL Procedure - PAL_VP_REGISTER.
Register a different host IVT and/or a different optional virtualization intercept handler for the virtual processor specified by vpd. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_REGISTER within the list of PAL procedures. | |
Vpd | 64-bit host virtual pointer to the Virtual Processor Descriptor (VPD) host_iva 64-bit host virtual pointer to the host IVT for the virtual processor | |
OptionalHandler | 64-bit non-zero host-virtual pointer to an optional handler for virtualization intercepts. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_VP_RESTORE 270 |
PAL Procedure - PAL_VP_RESTORE.
Restores virtual processor state for the specified vpd on the logical processor. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_RESTORE within the list of PAL procedures. | |
Vpd | 64-bit host virtual pointer to the Virtual Processor Descriptor (VPD) host_iva 64-bit host virtual pointer to the host IVT for the virtual processor | |
PalVector | Vector specifies PAL procedure implementation-specific state to be restored. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_VP_SAVE 271 |
PAL Procedure - PAL_VP_SAVE.
Saves virtual processor state for the specified vpd on the logical processor. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_SAVE within the list of PAL procedures. | |
Vpd | 64-bit host virtual pointer to the Virtual Processor Descriptor (VPD) host_iva 64-bit host virtual pointer to the host IVT for the virtual processor | |
PalVector | Vector specifies PAL procedure implementation-specific state to be restored. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |
#define PAL_VP_TERMINATE 272 |
PAL Procedure - PAL_VP_TERMINATE.
Terminates operation for the specified virtual processor. It is optional by Itanium processors. The PAL procedure supports the Stacked Registers calling convention. It could be called at Virtual mode.
Index | Index of PAL_VP_TERMINATE within the list of PAL procedures. | |
Vpd | 64-bit host virtual pointer to the Virtual Processor Descriptor (VPD) | |
Iva | Optional 64-bit host virtual pointer to the IVT when this procedure is done. |
0 | Call completed without error | |
-1 | Unimplemented procedure | |
-2 | Invalid argument | |
-3 | Call completed with error. | |
-9 | Call requires PAL memory buffer. |