Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100 |
#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20 |
#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24 |
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20 |
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28 |
#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E |
#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F |
#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20 |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A |
#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16 |
#define GET_NUMBER_RESIZABLE_BARS | ( | x | ) | (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5) |
#define GET_TPH_TABLE_SIZE | ( | x | ) | ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16) |
#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL | ( | ACS_EXTENDED | ) | (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020)) |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE | ( | ACS_EXTENDED | ) | (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00)) |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX | ( | POWER | ) | (UINT16)(((POWER->DpaCapability)&0x0000000F)) |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT | ( | LINK_DECLARATION | ) | (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8) |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE | ( | VENDOR | ) | (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20) |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009 |
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1 |
typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY |